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| 20 PRELIMINARY CY53120 Neuron Chip Network Processor Features * Maximum clock operation of 20 MHz, over a -40 to 85C temperature range * Three 8-bit pipelined processors for concurrent processing of application code and network packets * 11-pin I/O port programmable in 34 modes for fast application program development * Two 16-bit timer/counters for measuring and generating I/O device waveforms * 5-pin communication port that supports direct connect and network transceiver interfaces * 2048 bytes of SRAM for buffering network data and storing network variables * 2048 bytes of EEPROM memory for flexible storage of application code and configuration data * 10 KB of ROM for storing LonTalk network protocol firmware * Programmable pull-ups on IO4-IO7 and 20-mA sink current on IO0-IO3 * Unique 48-bit ID number in every device to facilitate network installation and management * 32-pin SOIC or 44-pin QFP packages * Low operating current. Sleep mode operation for reduced current consumption * On-chip LVD circuit to prevent non-volatile memory corruption during voltage drops * 0.35-m Flash process technology * 5.0V operation Functional Description The CY53120 is a Neuron(R) Chip which implements a node for the LonWorks(R) distributed intelligent control networks. It incorporates, on a single chip, the necessary communication and control functions, both in hardware and firmware, that facilitate the design of a LonWorks node. The CY53120 is manufactured using the state-of-the-art 0.35-m Flash technology, providing to the designers the most cost-effective Neuron Chip solution. Services at every layer of the OSI networking reference model are implemented in the LonTalk firmware-based protocol stored in the 10-KB ROM. In addition, the ROM firmware also contains preprogrammed I/O drivers, greatly simplifying application programming. The application program is stored in the EEPROM memory, and may be updated by downloading over the network. The CY53120 contains a very flexible 5-pin communication port, that can be configured to interface to a wide variety of media transceivers at a wide range of data rates. The most common transceiver types are: twisted-pair, powerline, RF, IR, fiber-optics, and coaxial. The CY53120 Neuron Chip is fully compatible with the Motorola MC143120E2 device. Logic Block Diagram Media Access Control Processor Network Processor Application Processor 2 KB RAM Internal Data Bus (0:7) Internal Address Bus (0:15) Communication Port I/O Block 2 Timer/ Counters CP4 CP0 IO10 IO0 2 KB EEPROM Oscillator, Clock, and Control CLK1 CLK2 /SERVICE /RESET 10 KB ROM LVD Echelon, LonWorks, LonBuilder, LonTalk, NodeBuilder, and Neuron are registered trademarks of Echelon Corporation. Cypress Semiconductor Corporation * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 January 6, 2000, rev. ** |
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